 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter DESCRIPTION The LF3310 is a two-dimensional digital image filter capable of filtering data at real-time video rates. The device contains both a horizontal and a vertical filter which may be cascaded or used concurrently for two-dimensional filtering. The input, coefficient, and output data are all 12-bits and in two's complement format. The horizontal filter is designed to take advantage of symmetric coefficient sets. When symmetric coefficient sets are used, the horizontal filter can be configured as a 16-tap FIR filter. When asymmetric coefficient sets are used, it can be configured as an 8-tap FIR filter. The vertical filter is an 8-tap FIR filter with all required line buffers contained on-chip. The line buffers can store video lines with lengths from 4 to 3076 pixels. Horizontal filter Interleave/Decimation Registers (I/D Registers) and the vertical filter line buffers allow interleaved data to be fed directly into the device and filtered without separating the data into individual data streams. The horizontal filter can handle a maximum of sixteen data sets interleaved together. The vertical filter can handle interleaved video lines which contain 3076 or less data values. The I/D Registers and horizontal accumulator facilitate using decimation to increase the number of filter taps in the horizontal filter. Decimation of up to 16:1 is supported. The device has on-chip storage for 256 horizontal coefficient sets and 256 vertical coefficient sets. Each filter's coefficients are loaded independently of each other allowing one filter's coefficients to be updated without affecting the other filter's coefficients. In addition, a horizontal or vertical coefficient set can be updated independently from the other coefficient sets in the same filter. FEATURES u 83 MHz Data Rate u 12-bit Data and Coefficients u On-board Memory for 256 Horizontal and Vertical Coefficient Sets u LF InterfaceTM Allows All 512 Coefficient Sets to be Updated Within Vertical Blanking u Selectable 12-bit Data Output with User-Defined Rounding and Limiting u Seven 3K x 12-bit, Programmable Two-Mode Line Buffers u 16 Horizontal Filter Taps u 8 Vertical Filter Taps u Two Operating Modes: Dimensionally Separate and Orthogonal u Supports Interleaved Data Streams u Horizontal Filter Supports Decimation up to 16:1 for Increasing Number of Filter Taps u 3.3 Volt Power Supply u 5 Volt Tolerant I/O u 144 Lead PQFP LF3310 BLOCK DIAGRAM 12 DIN11-0 16-TAP HORIZONTAL FILTER 256 COEFFICIENT SET STORAGE 3K LINE BUFFER 3K LINE BUFFER 3K LINE BUFFER 3K LINE BUFFER 3K LINE BUFFER 3K LINE BUFFER 8-TAP VERTICAL FILTER 256 COEFFICIENT SET STORAGE 12 3K LINE BUFFER DOUT11-0 Video Imaging Products 1 11/08/2001-LDS.3310-H I/D REGISTERS FIGURE 1. EOI DATA REVERSAL 1-16 1-16 1-16 1-16 1-16 1-16 1-16 TXFR DATA DELAY 12 1-16 1-16 1-16 1-16 1-16 1-16 1-16 DEVICES INCORPORATED 12 ALU 13 ALU 13 ALU 13 ALU 13 ALU 13 ALU 13 ALU 13 ALU 13 A B A B A B A B A B A B A B 1-16 A DIN11-0 B HCF11-0 HPAUSE HLD 12 H Coef Bank 0 CONFIGURATION AND CONTROL REGISTERS 12 H Coef Bank 1 12 12 HORIZONTAL LF INTERFACE 12 VCF11-0 H Coef Bank 7 VPAUSE VLD VERTICAL LF INTERFACE H Coef Bank 6 HCEN 12 H Coef Bank 2 12 H Coef Bank 5 8 HCA7-0 VCEN 12 H Coef Bank 3 12 H Coef Bank 4 8 VCA7-0 25 25 25 25 25 25 25 25 V Coef Bank 7 27 V Coef Bank 6 V Coef Bank 5 V Coef Bank 4 27 LF3310 FUNCTIONAL BLOCK DIAGRAM 12 12 24 12 12 12 2 HACC 12 26 12 24 24 "0" 32 12 24 DATA DELAY 12 24 32 12 24 26 12 24 "0" 32 32 4 HRSL3-0 VERTICAL ROUND SELECT LIMIT HORIZONTAL ROUND SELECT LIMIT 12 24 12 12 12 12 12 V Coef Bank 0 V Coef Bank 1 V Coef Bank 2 V Coef Bank 3 OE 4 VACC VRSL3-0 12 DOUT11-0 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer 3K Line Buffer HSHEN VSHEN Horizontal / Vertical Digital Image Filter Video Imaging Products LF3310 11/08/2001-LDS.3310-H CLK LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter FIGURE 2. INPUT FORMATS Input Data 11 10 9 -211 210 29 (Sign) SIGNAL DEFINITIONS Power VCC and GND +3.3 V power supply. All pins must be connected. Clock CLK -- Master Clock The rising edge of CLK strobes all enabled registers. Inputs DIN11-0 -- Data Input DIN11-0 is the 12-bit registered data input port. Data is latched on the rising edge of CLK. HCF11-0 -- Horizontal Coefficient Input HCF11-0 is used to load data into the horizontal coefficient banks and the Configuration/Control Registers. Data present on HCF11-0 is latched into the Horizontal LF InterfaceTM on the rising edge of CLK when HLD is LOW (see the LF InterfaceTM section for a full discussion). HCA7-0 -- Horizontal Coefficient Address HCA7-0 determines which row of data in the horizontal coefficient banks is fed to the multipliers in the horizontal filter. HCA7-0 is latched into the Horizontal Coefficient Address Register on the rising edge of CLK when HCEN is LOW. VCF11-0 -- Vertical Coefficient Input VCF11-0 is used to load data into the vertical coefficient banks and the Configuration/Control Registers. Data present on VCF11-0 is latched into the Vertical LF InterfaceTM on the rising edge of CLK when VLD is LOW (see the LF InterfaceTM section for a full discussion). Coefficient Data 11 10 9 -20 2-1 2-2 (Sign) 210 22 21 20 210 2-9 2-10 2-11 FIGURE 3. HORIZONTAL AND VERTICAL ACCUMULATOR FORMATS Vertical Accumulator Output 31 30 29 -220 219 218 (Sign) Horizontal Accumulator Output 31 30 29 -220 219 218 (Sign) 210 2-9 2-10 2-11 210 2-9 2-10 2-11 TABLE 1. OUTPUT FORMATS SLCT4-0 00000 00001 00010 S11 S10 F11 F10 S9 F9 F12 F11 F10 F13 F12 F11 *** *** *** *** S6 F6 F7 F8 S5 F5 F6 F7 *** *** *** *** S2 F2 F3 F4 S1 F1 F2 F3 S0 F0 F1 F2 * * * 10010 10011 10100 * * * * * * * * * *** *** *** * * * * * * *** *** *** * * * * * * * * * F29 F28 F27 F30 F29 F28 F31 F30 F29 F24 F23 F25 F24 F26 F25 Controls F20 F19 F18 F21 F20 F19 F22 F21 F20 VCA7-0 -- Vertical Coefficient Address VCA7-0 determines which row of data in the vertical coefficient banks is fed to the multipliers in the vertical filter. VCA7-0 is latched into the Vertical Coefficient Address Register on the rising edge of CLK when VCEN is LOW. Outputs DOUT11-0 -- Data Output DOUT11-0 is the 12-bit registered data output port. HLD -- Horizontal Coefficient Load When HLD is LOW, data on HCF11-0 is latched into the Horizontal LF InterfaceTM on the rising edge of CLK. When HLD is HIGH, data can not be latched into the Horizontal LF InterfaceTM. When enabling the LF InterfaceTM for data input, a HIGH to LOW transition of HLD is required in order for the input circuitry to function properly. Therefore, HLD must be set HIGH immediately after power up to ensure proper operation of the input circuitry (see the LF InterfaceTM section for a full discussion). Video Imaging Products 3 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter HACC -- Horizontal Accumulator Control When HACC is HIGH, the horizontal accumulator is enabled for accumulation and the accumulator output register is disabled for loading. When HACC is LOW, no accumulation is performed and the accumulator output register is enabled for loading. HACC is latched on the rising edge of CLK. VACC -- Vertical Accumulator Control When VACC is HIGH, the vertical accumulator is enabled for accumulation and the accumulator output register is disabled for loading. When VACC is LOW, no accumulation is performed and the accumulator output register is enabled for loading. VACC is latched on the rising edge of CLK. HSHEN -- Horizontal Shift Enable HSHEN enables or disables the loading of data into the forward and reverse I/D Registers in the horizontal filter when the device is in Dimensionally Separate Mode. If the device is configured such that the horizontal filter feeds the vertical filter, HSHEN also enables or disables the loading of data into the input register (DIN11-0). If the device is configured such that the vertical filter feeds the horizontal filter and the vertical limit register is under shift control, HSHEN also enables or disables the loading of data into the vertical limit register in the vertical Round/Select/Limit circuitry. In Orthogonal Mode, HSHEN also enables or disables the loading of data into the input register (DIN11-0) and the line buffers in the vertical filter. It is important to note that in Orthogonal Mode, either HSHEN or VSHEN can disable data loading. Both must be active to enable data loading in Orthogonal Mode. Also in Orthogonal Mode, the horizontal and vertical limit registers can not be disabled. When HSHEN is LOW, data is loaded into and shifted through the registers HSHEN controls and the forward and reverse I/D Registers on the rising edge of CLK. When HSHEN is HIGH, data is not loaded into or shifted through the registers HSHEN controls and the I/D Registers, and their contents will not be changed. HSHEN is latched on the rising edge of CLK. VSHEN -- Vertical Shift Enable VSHEN enables or disables the loading of data into the line buffers in the vertical filter when the device is in Dimensionally Separate Mode. If the device is configured such that the vertical filter feeds the horizontal filter, VSHEN also enables or disables the loading of data into the input register (DIN11-0). If the device is configured such that the horizontal filter feeds the vertical filter and the horizontal limit register is under shift control, VSHEN also enables or disables the loading of data into the horizontal limit register in the horizontal Round/Select/Limit circuitry. In Orthogonal Mode, VSHEN also enables or disables the loading of data into the input register (DIN11-0) and the forward and reverse I/D Registers in the horizontal filter. It is important to note that in Orthogonal Mode, either HSHEN or VSHEN can disable data loading. Both must be active to enable data loading in Orthogonal Mode. Also in Orthogonal Mode, the horizontal and vertical limit registers can not be disabled. When VSHEN is LOW, data is loaded into and shifted through the registers VSHEN controls and the line buffers on the rising edge of CLK. When VSHEN is HIGH, data is not loaded into or shifted through the registers VSHEN controls and the line buffers, and their contents will not be changed. VSHEN is latched on the rising edge of CLK. HCEN -- Horizontal Coefficient Address Enable When HCEN is LOW, data on HCA7-0 is latched into the Horizontal Coefficient Address Register on the rising edge of CLK. When HCEN is HIGH, data on HCA7-0 is not latched and the register's contents will not be changed. VLD -- Vertical Coefficient Load When VLD is LOW, data on VCF11-0 is latched into the Vertical LF InterfaceTM on the rising edge of CLK. When VLD is HIGH, data can not be latched into the Vertical LF InterfaceTM. When enabling the LF InterfaceTM for data input, a HIGH to LOW transition of VLD is required in order for the input circuitry to function properly. Therefore, VLD must be set HIGH immediately after power up to ensure proper operation of the input circuitry (see the LF InterfaceTM section for a full discussion). VCEN -- Vertical Coefficient Address Enable When VCEN is LOW, data on VCA7-0 is latched into the Vertical Coefficient Address Register on the rising edge of CLK. When VCEN is HIGH, data on VCA7-0 is not latched and the register's contents will not be changed. TXFR -- Horizontal Filter LIFO Transfer Control TXFR is used to change which LIFO in the data reversal circuitry sends data to the reverse data path and which LIFO receives data from the forward data path. When TXFR goes LOW, the LIFO sending data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The device must see a HIGH to LOW transition of TXFR in order to switch LIFOs. Video Imaging Products 4 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter FIGURE 4. DIMENSIONALLY SEPARATE MODE: H TO V 12 DIN11-0 HORIZONTAL FILTER HRSL3-0 -- Horizontal Round/Select/ Limit Control HRSL3-0 determines which of the sixteen user-programmable Round/ Select/Limit registers (RSL registers) are used in the horizontal Round/ Select/Limit circuitry (RSL circuitry). A value of 0 on HRSL3-0 selects RSL register 0. A value of 1 selects round/select/limit register 1 and so on. HRSL3-0 is latched on the rising edge of CLK (see the horizontal round, select, and limit sections for a complete discussion). VRSL3-0 --Vertical Round/Select/Limit Control VRSL3-0 determines which of the sixteen user-programmable RSL registers are used in the vertical RSL circuitry. A value of 0 on VRSL3-0 selects RSL register 0. A value of 1 selects RSL register 1 and so on. VRSL3-0 is latched on the rising edge of CLK (see the vertical round, select, and limit sections for a complete discussion). OE -- Output Enable When OE is LOW, DOUT11-0 is enabled for output. When OE is HIGH, DOUT11-0 is placed in a high-impedance state. HPAUSE -- LF InterfaceTM Pause When HPAUSE is HIGH, the Horizontal LF Interface TM loading sequence is halted until HPAUSE is returned to a LOW state. This effectively allows the user to load coefficients and Control Registers at a slower rate than the master clock (see the LF InterfaceTM section for a full discussion). VPAUSE -- LF InterfaceTM Pause When VPAUSE is HIGH, the Vertical LF InterfaceTM loading sequence is halted until VPAUSE is returned to a LOW state. This effectively allows the user to load coefficients and Control 12 LINE BUFFER LINE BUFFER VERTICAL FILTER LINE BUFFER 12 DOUT11-0 LINE BUFFER LINE BUFFER LINE BUFFER LINE BUFFER FIGURE 5. 12 DIN11-0 DIMENSIONALLY SEPARATE MODE: V TO H LINE BUFFER LINE BUFFER LINE BUFFER VERTICAL FILTER 12 HORIZONTAL FILTER LINE BUFFER LINE BUFFER 12 LINE BUFFER LINE BUFFER DOUT11-0 Registers at a slower rate than the master clock (see the LF InterfaceTM section for a full discussion). OPERATIONAL MODES Dimensionally Separate In Dimensionally Separate Mode, the horizontal and vertical filters are cascaded together to form a two-dimensional image filter (see Figures 4 and 5). Bit 1 in Configuration Register 4 determines the cascade order. If this bit is set to "0", data on DIN11-0 is fed into the horizontal filter first. The horizontal filter then feeds data into the vertical filter. If this bit is set to "1", data on DIN11-0 is fed into the vertical filter first. The vertical filter then feeds data into the horizontal filter. Orthogonal In Orthogonal Mode, the horizontal and vertical filters are used concurrently to implement an orthogonal kernel on the input data (see Figure 6). Video Imaging Products 5 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter and vertical filters will not line up correctly because the data delays are calculated assuming that the first 3, 5, or 7 multipliers are used. Also, the ALUs in the horizontal filter should be configured to accept data from the forward I/D Register path into ALU Input A and force ALU Input B to 0. FUNCTIONAL DESCRIPTION VERTICAL FILTER FIGURE 6. DIN11-0 ORTHOGONAL MODE 12 DATA DELAY HORIZONTAL FILTER LINE BUFFER LINE BUFFER Horizontal Filter DATA DELAY LINE BUFFER LINE BUFFER LINE BUFFER 12 LINE BUFFER LINE BUFFER The horizontal filter is designed to filter a digital image in the horizontal dimension. This FIR filter can be configured to have as many as 16-taps when symmetric coefficient sets are used and 8-taps when asymmetric coefficient sets are used. ALUs DOUT11-0 FIGURE 7. 3-3, 5-5, AND 7-7 ORTHOGONAL KERNELS V1 V1 V2 V3 H1 H2 H3 HV4 H5 H6 H7 V5 V6 V7 V1 H1 HV2 H3 V3 V2 H1 H2 HV3 H4 H5 V4 V5 The HV Filter can handle kernel sizes of 3-3, 5-5, and 7-7 (see Figure 7). Data delay elements at the input of the horizontal filter and the output of the vertical filter are used to properly align data so that the orthogonal kernel is implemented correctly. The data delays are automatically set to the correct lengths based on the programmed length of the line buffers and the kernel size. Kernel sizes of 3-3, 5-5, and 7-7 require that the horizontal filter's output be delayed by LB - 2, 2(LB) - 3, and 3(LB) - 4 clock cycles respectively before being added to the vertical filter's output (LB is the programmed line buffer length). The data delay at the input of the horizontal filter handles the LB, 2(LB), and 3(LB) delays. The data delay at the output of the vertical filter handles the - 2, - 3, and - 4 delays. For example, if the line buffers are programmed for a length of 720 and a 5-5 kernel is selected, the horizontal filter input data delay will be 1440 clock cycles and the vertical filter output data delay will be 3 clock cycles. It is important to note that the first 3, 5, or 7 multipliers of the horizontal and vertical filters must be used in Orthogonal Mode. If other multipliers are used, data from the horizontal The ALUs double the number of filter taps available, when symmetric coefficient sets are used, by pre-adding data values which are then multiplied by a common coefficient (see Figure 8). The ALUs can perform two operations: A+B and B-A. Bit 0 of Configuration Register 0 determines the ALU operation. A+B is used with even-symmetric coefficient sets. B-A is used with odd-symmetric coefficient sets. Also, either the A or B operand may be set to 0. Bits 1 and 2 of Configuration Register 0 control the ALU inputs. A+0 or B+0 are used with asymmetric coefficient sets. Interleave/Decimation Registers The Interleave/Decimation Registers (I/D Registers) feed the ALU inputs. They allow the device to filter up to sixteen data sets interleaved into the same data stream without having to separate the data sets. The I/D Registers should be set to a length equal to the number of data sets interleaved together. For example, if two data sets are interleaved together, the I/D Registers should be set to a length of two. Bits 1 through 4 of Configuration Register 1 determine Video Imaging Products 6 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter FIGURE 8. SYMMETRIC COEFFICIENT SET EXAMPLES 8765 87654321 7654321 4321 Even-Tap, Even-Symmetric Coefficient Set Odd-Tap, Even-Symmetric Coefficient Set Even-Tap, Odd-Symmetric Coefficient Set FIGURE 9. I/D REGISTER DATA PATHS DATA REVERSAL DATA REVERSAL DATA REVERSAL 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 1-16 Delay Stage N-1 Delay Stage N A ALU B A ALU B A ALU B A ALU B A ALU B 1-16 A the I/D Register length. The I/D Registers also facilitate using decimation to increase the number of filter taps. Decimation by N is accomplished by reading the horizontal filter's output once every N clock cycles. The device supports decimation up to 16:1. With no decimation, the maximum number of filter taps is sixteen. When decimating by N, the number of filter taps becomes 16N because there are N-1 clock cycles when the horizontal filter's output is not being read. The extra clock cycles are used to calculate more filter taps. When decimating, the I/D Registers should be set to a length equal to the decimation factor. For example, when performing a 4:1 decimation, the I/D Registers should be set to a 1-16 EVEN-TAP MODE 1-16 ALU B COEF 7 COEF 6 COEF 7 2 COEF 6 COEF 7 2 COEF 6 ODD-TAP MODE ODD-TAP INTERLEAVE MODE length of four. When not decimating or when only one data set (non-interleaved data) is fed into the device, the I/D Registers should be set to a length of one. HSHEN enables or disables the loading of data into the forward and reverse I/D Registers when the device is in Dimensionally Separate Mode (see the HSHEN section for a full discussion). When in Orthogonal Mode, HSHEN also enables or disables the loading of data into the input register (DIN11-0) and the line buffers. It is important to note that in Orthogonal Mode, either HSHEN or VSHEN can disable the loading of data into the input register (DIN11-0), I/D Registers, and line buffers. Both must be active to enable data loading in Orthogonal Mode. I/D Register Data Path Control The multiplexer in the middle of the I/D Register data path controls how data is fed to the reverse data path. The forward data path contains the I/D Registers in which data flows from left to right in the block diagram in Figure 1. The reverse data path contains the I/D Registers in which data flows from right to left. When the filter is configured for an even number of taps, data from the last I/D Register in the forward data path is fed into the first I/D Register in the reverse data path (see Figure 9). Video Imaging Products 7 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter Data Reversal Data reversal circuitry is placed after the multiplexer which routes data from the forward data path to the reverse data path (see Figure 10). When decimating, the data stream must be reversed in order for data to be properly aligned at the inputs of the ALUs. When data reversal is enabled, the circuitry uses a pair of LIFOs to reverse the order of the data sent to the reverse data path. When TXFR goes LOW, the LIFO sending data to the reverse data path becomes the LIFO receiving data from the forward data path, and the LIFO receiving data from the forward data path becomes the LIFO sending data to the reverse data path. The device must see a HIGH to LOW transition of TXFR in order to switch LIFOs. If decimating by N, TXFR should go low once every N clock cycles. When data reversal is disabled, the circuitry functions like an I/D Register. When feeding interleaved data through the filter, data reversal should be disabled. Bit 6 of Configuration Register 1 enables or disables data reversal. Horizontal Rounding The horizontal filter output may be rounded by adding the contents of one of the sixteen horizontal round registers to the horizontal filter output FIGURE 10. DATA REVERSAL TXFR LIFO A LIFO B 1-16 When the filter is configured for an odd number of taps, the data which will appear at the output of the last I/D Register in the forward data path on the next clock cycle is fed into the first I/D Register in the reverse data path. Bit 5 in Configuration Register 1 configures the filter for an even or odd number of taps. When interleaved data is fed through the device and an even tap filter is desired, the filter should be configured for an even number of taps (Bit 5 of CR1 set to "0") and the I/D Register length should match the number of data sets interleaved together. When interleaved data is to be fed through the device and an odd tap filter is desired, the filter should be set to Odd-Tap Interleave Mode. Bit 0 of Configuration Register 1 configures the filter for Odd-Tap Interleave Mode. When the filter is configured for Odd-Tap Interleave Mode, data from the next to last I/D Register in the forward data path is fed into the first I/D Register in the reverse data path. When the filter is configured for an odd number of taps (interleaved or non-interleaved modes), the filter is structured such that the center data value is aligned simultaneously at the A and B inputs of the last ALU in the forward data path. In order to achieve the correct result, the user must divide the coefficient by two. FIGURE 11. HORIZONTAL AND VERTICAL ROUND/SELECT/LIMIT CIRCUITRY VRSL3-0 4 DATA IN 32 DATA IN 32 HRSL3-0 4 32 RND RND 32 32 32 5 SELECT SELECT 5 12 12 24 LIMIT LIMIT 24 VERTICAL RSL 12 DATA OUT 12 DATA OUT HORIZONTAL RSL Video Imaging Products 8 11/08/2001-LDS.3310-H LH15 LV15 LH0 LV0 SH15 SV15 SH0 SV0 RH15 RV15 RH0 RV0 LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter Horizontal Select The word width of the horizontal filter output is 32-bits. However, only 12-bits may be sent to the filter output. The horizontal filter select circuitry determines which 12-bits are passed (see Table 1). The horizontal select registers control the horizontal select circuitry. There are sixteen horizontal select registers. Each select register is 5-bits wide and userprogrammable. HRSL3-0 determines which of the sixteen horizontal select registers are used in the horizontal select circuitry. A value of 0 on HRSL3-0 selects horizontal select register 0. A value of 1 selects horizontal select register 1 and so on. HRSL3-0 may be changed every clock cycle if desired. This allows the 12-bit window to be changed every clock cycle. This is useful when filtering interleaved data. Select register loading is discussed in the LF InterfaceTM section. Horizontal Limiting An output limiting function is provided for the output of the horizontal filter. The horizontal limit registers determine the valid range of output values when limiting is enabled (Bit 1 in Configuration Register 5). There are sixteen 24-bit horizontal limit registers. HRSL3-0 determines which horizontal limit register is used during the limit operation. A value of 0 on HRSL3-0 selects horizontal limit register 0. A value of 1 selects horizontal limit register 1 and so on. Each limit register contains both an upper and lower limit value. If the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the filter output. If the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is passed as the filter output. HRSL3-0 may be changed every clock cycle if desired. This allows the limit range to be TABLE 2. CONFIGURATION REGISTER 0 - ADDRESS 200H BITS 0 1 2 11-3 FUNCTION ALU Mode Pass A Pass B Reserved DESCRIPTION 0: A + B 1: B - A 0 : ALU Input A = 0 1 : ALU Input A = Forward Register Path 0 : ALU Input B = 0 1 : ALU Input B = Reverse Register Path Must be set to "0" TABLE 3. CONFIGURATION REGISTER 1 - ADDRESS 201H BITS 0 4-1 FUNCTION Odd-Tap Interleave Mode I/D Register Length DESCRIPTION 0 : Odd-Tap Interleave Mode Disabled 1 : Odd-Tap Interleave Mode Enabled 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: 1 Register 2 Registers 3 Registers 4 Registers 5 Registers 6 Registers 7 Registers 8 Registers 9 Registers 10 Registers 11 Registers 12 Registers 13 Registers 14 Registers 15 Registers 16 Registers 5 6 11-7 Horizontal Tap Number Horizontal Data Reversal Reserved 0 : Even Number of Taps 1 : Odd Number of Taps 0 : Data Reversal Enabled 1 : Data Reversal Disabled Must be set to "0" (see Figure 11). Each round register is 32-bits wide and user-programmable. This allows the filter's output to be rounded to any precision required. Since any 32-bit value may be programmed into the round registers, the device can support complex rounding algorithms as well as standard Half-LSB rounding. HRSL30 determines which of the sixteen horizontal round registers are used in the rounding operation. A value of 0 on HRSL3-0 selects horizontal round register 0. A value of 1 selects horizontal round register 1 and so on. HRSL3-0 may be changed every clock cycle if desired. This allows the rounding algorithm to be changed every clock cycle. This is useful when filtering interleaved data. If rounding is not desired, a round register should be loaded with 0 and selected as the register used for rounding. Round register loading is discussed in the LF InterfaceTM section. Video Imaging Products 9 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter section for a full discussion). When in Orthogonal Mode, VSHEN also enables or disables the loading of data into the input register (DIN11-0) and the forward and reverse I/D Registers. It is important to note that in Orthogonal Mode, either HSHEN or VSHEN can disable the loading of data into the input register (DIN11-0), I/D Registers, and line buffers. Both must be active to enable data loading in Orthogonal Mode. Interleaved Data The vertical filter is capable of handling interleaved data. The number of data sets it can handle is determined by the number of data values contained in a video line. If the interleaved video line has 3076 data values or less, the vertical filter can handle it no matter how many data sets are interleaved together. changed every clock cycle. This is useful when filtering interleaved data. When loading limit values into the device, the upper limit must be greater than the lower limit. Limit register loading is discussed in the LF InterfaceTM section. Vertical Filter The vertical filter is designed to filter a digital image in the vertical dimension. It is a FIR filter which can be configured to have as many as 8-taps. Line Buffers There are seven on-chip line buffers. The maximum delay length of each line buffer is 3076 cycles and the minimum is 4 cycles. Configuration Register 2 (CR2) determines the delay length of the line buffers. The line buffer length is equal to the value of CR2 plus 4. A value of 0 for CR2 sets the line buffer length to 4. A value of 3072 for CR2 sets the line buffer length to 3076. Any values for CR2 greater than 3072 are not valid. The line buffers have two modes of operation: delay mode and recirculate mode. Bit 0 of Configuration Register 3 determines which mode the line buffers are in. In delay mode, the data input to the line buffer is delayed by an amount determined by CR2. In recirculate mode, the output of the line buffer is routed back to the input of the line buffer allowing the line buffer contents to be read multiple times. Bit 1 of Configuration Register 3 allows the line buffers to be loaded in parallel. When Bit 1 is "1", the input register (DIN11-0) loads all seven line buffers in parallel. This allows all the line buffers to be preloaded with data in the amount of time it normally takes to load a single line buffer. VSHEN enables or disables the loading of data into the line buffers when the device is in Dimensionally Separate Mode (see the VSHEN TABLE 4. CONFIGURATION REGISTER 2 - ADDRESS 202H BITS 11-0 FUNCTION Line Buffer Length DESCRIPTION See Line Buffer Description Section TABLE 5. CONFIGURATION REGISTER 3 - ADDRESS 203H BITS 0 1 11-2 FUNCTION Line Buffer Mode Line Buffer Load Reserved DESCRIPTION 0 : Delay Mode 1 : Recirculate Mode 0 : Normal Load 1 : Parallel Load Must be set to "0" TABLE 6. CONFIGURATION REGISTER 4 - ADDRESS 204H BITS 0 1 3-2 FUNCTION HV Filter Mode HV Direction Orthogonal Kernel Size DESCRIPTION 0 : Orthogonal Mode 1 : Dimensionally Separate 0 : Horizontal to Vertical 1 : Vertical to Horizontal 00 : 01 : 10 : 11 : 3-3 Kernel 5-5 Kernel 7-7 Kernel Not Used 4 11-5 Limit Register Load Control Reserved 0 : Limit Registers Always Enabled 1 : Limit Registers Under Shift Enable Control Must be set to "0" TABLE 7. CONFIGURATION REGISTER 5 - ADDRESS 205H BITS 0 1 11-2 FUNCTION Vertical Limit Enable Horizontal Limit Enable Reserved DESCRIPTION 0 : Vertical Limiting Disabled 1 : Vertical Limiting Enabled 0 : Horizontal Limiting Disabled 1 : Horizontal Limiting Enabled Must be set to "0" Video Imaging Products 10 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter TABLE 9. HRZ. ROUND REGISTERS REGISTER 0 1 ADDRESS (HEX) 800 801 TABLE 8. HCF/VCF11-9 DECODE 11 10 9 DESCRIPTION 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Coefficient Banks Configuration Registers Horizontal Select Registers Vertical Select Registers Horizontal Round Registers Vertical Round Registers Horizontal Limit Registers Vertical Limit Registers TABLE 12. VRT. ROUND REGISTERS REGISTER 0 1 ADDRESS (HEX) A00 A01 14 15 80E 80F 14 15 A0E A0F TABLE 10. HRZ. SELECT REGISTERS REGISTER 0 1 ADDRESS (HEX) 400 401 TABLE 13. VRT. SELECT REGISTERS REGISTER 0 1 ADDRESS (HEX) 600 601 Vertical Rounding The vertical filter output may be rounded by adding the contents of one of the sixteen vertical round registers to the vertical filter output (see Figure 11). Each round register is 32-bits wide and user-programmable. This allows the filter's output to be rounded to any precision required. Since any 32-bit value may be programmed into the round registers, the device can support complex rounding algorithms as well as standard Half-LSB rounding. VRSL3-0 determines which of the sixteen vertical round registers are used in the rounding operation. A value of 0 on VRSL3-0 selects vertical round register 0. A value of 1 selects vertical round register 1 and so on. VRSL3-0 may be changed every clock cycle if desired. This allows the rounding algorithm to be changed every clock cycle. This is useful when filtering interleaved data. If rounding is not desired, a round register should be loaded with 0 and selected as the register used for rounding. Round register loading is discussed in the LF InterfaceTM section. Vertical Select The word width of the vertical filter output is 32-bits. However, only 12-bits may be sent to the filter output. The vertical filter select circuitry determines which 12-bits are passed (see Table 1). The vertical select registers control the vertical select circuitry. There are sixteen vertical select registers. Each select 14 15 40E 40F 14 15 60E 60F TABLE 11. HRZ. LIMIT REGISTERS REGISTER 0 1 ADDRESS (HEX) C00 C01 TABLE 14. VRT. LIMIT REGISTERS REGISTER 0 1 ADDRESS (HEX) E00 E01 14 15 C0E C0F 14 15 E0E E0F register is 5-bits wide and user-programmable. VRSL3-0 determines which of the sixteen vertical select registers are used in the vertical select circuitry. A value of 0 on VRSL3-0 selects vertical select register 0. A value of 1 selects vertical select register 1 and so on. VRSL3-0 may be changed every clock cycle if desired. This allows the 12-bit window to be changed every clock cycle. This is useful when filtering interleaved data. Select register loading is discussed in the LF InterfaceTM section. Vertical Limiting An output limiting function is provided for the output of the vertical filter. The vertical limit registers determine the valid range of output values when limiting is enabled (Bit 0 in Configuration Register 5). There are sixteen 24-bit vertical limit registers. VRSL3-0 determines which vertical limit register is used during the limit operation. A value of 0 on VRSL3-0 selects vertical limit register 0. A value of 1 selects vertical limit register 1 and so on. Each limit register contains both an upper and lower limit value. If the value fed to the limiting circuitry is less than the lower limit, the lower limit value is passed as the filter output. If the value fed to the limiting circuitry is greater than the upper limit, the upper limit value is passed as the filter output. VRSL3-0 may be changed every clock cycle if desired. This allows the limit range to be changed every clock cycle. This is useful when filtering interleaved data. When loading limit values into the device, the upper limit must be greater than the lower limit. Limit register loading is discussed in the LF InterfaceTM section. Video Imaging Products 11 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter FIGURE 12. COEFFICIENT BANK LOADING SEQUENCE COEFFICIENT SET 1 COEFFICIENT SET 2 COEFFICIENT SET 3 CLK W1 HLD/VLD W2 W3 HCF/VCF11-0 ADDR1 COEF0 COEF7 ADDR2 COEF0 COEF7 ADDR3 COEF0 COEF7 W1: Coefficient Set 1 written to coefficient banks during this clock cycle. W2: Coefficient Set 2 written to coefficient banks during this clock cycle. W3: Coefficient Set 3 written to coefficient banks during this clock cycle. FIGURE 13. CONFIGURATION/CONTROL REGISTER LOADING SEQUENCE CONFIG REG SELECT REG ROUND REGISTER LIMIT REGISTER CLK W1 HLD/VLD W2 W3 W4 HCF/VCF11-0 ADDR1 DATA1 ADDR2 DATA1 ADDR3 DATA1 DATA2 DATA3 DATA4 ADDR4 DATA1 DATA2 W1: Configuration Register loaded with new data on this rising clock edge. W2: Select Register loaded with new data on this rising clock edge. W3: Round Register loaded with new data on this rising clock edge. W4: Limit Register loaded with new data on this rising clock edge. Coefficient Banks The coefficient banks store the coefficients which feed into the multipliers in the horizontal and vertical filters. There is a separate bank for each multiplier. Each bank can hold 256 12-bit coefficients. The banks are loaded using an LF InterfaceTM. There is a separate LF InterfaceTM for the horizontal and vertical banks. Coefficient bank loading is discussed in the LF InterfaceTM section. Configuration and Control Registers The Configuration Registers determine how the HV Filter operates. Tables 2 through 7 show the formats of the six configuration registers. There are three types of control registers: round, select, and limit. There are sixteen round registers for the horizontal filter and sixteen for the vertical filter. Each register is 32-bits wide. HRSL3-0 and VRSL3-0 determine which horizontal and vertical round registers respectively are used for rounding. There are sixteen select registers for the horizontal filter and sixteen for the vertical filter. Each register is 5-bits wide. HRSL3-0 and VRSL3-0 determine which horizontal and vertical select registers respectively are used in the select circuitry. There are sixteen limit registers for the horizontal filter and sixteen for the vertical filter. Each register is 24-bits wide and stores both an upper and lower limit value. The lower limit is stored in bits 11-0 and the upper limit is stored in bits 23-12. HRSL3-0 and VRSL3-0 determine which horizontal and vertical limit registers respectively are used for limiting when limiting is enabled. Configuration and Control Register loading is discussed in the LF InterfaceTM section. LF InterfaceTM The Horizontal and Vertical LF InterfacesTM are used to load data into the horizontal and vertical coefficient banks respectively. They are also used to load data into the Configuration and Control Registers. The following section describes how the Horizontal LF InterfaceTM works. The Horizontal and Vertical LF InterfacesTM are identical in function. If HLD and HCF11-0 are replaced with VLD and VCF11-0, the following section will describe how the Vertical LF InterfaceTM works. HLD is used to enable and disable the Horizontal LF InterfaceTM. When Video Imaging Products 12 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter The next value(s) loaded into the interface are the data value(s) which will be stored in the bank or register defined by the address value. When loading coefficient banks, the interface will expect eight values to be loaded into the device after the address value. The eight values are coefficients 0 through 7. When loading select or Configuration Registers, the interface will expect one value after the address value. When loading round registers, the interface will expect four values after the address value. When loading limit registers, the interface will expect two values after the address value. Figures 12 and 13 show the data loading sequences for the coefficient banks and Configuration/Control Registers. Both HPAUSE and VPAUSE allow the user to effectively slow the rate of data loading through the LF InterfaceTM. When HPAUSE is HIGH, the LF InterfaceTM affecting the data used for the Horizontal Filter is held until HPAUSE is returned to a LOW. When VPAUSE is HIGH, the LF InterfaceTM affecting the data used for the Vertical Filter is held until VPAUSE is returned to a LOW. Figures 14 through 17 display the effects of both HPAUSE and VPAUSE while loading coefficient and control data. Table 15 shows an example of loading data into the coefficient banks. The following data values are written into address 10 of coefficient banks 0 through 7: 210H, 543H, C76H, 9E3H, 701H, 832H, F20H, 143H. Table 16 HLD goes LOW, the Horizontal LF InterfaceTM is enabled for data input. The first value fed into the interface on HCF11-0 is an address which determines what the interface is going to load. The three most significant bits (HCF11-9) determine if the LF InterfaceTM will load coefficient banks or Configuration/Control Registers (see Table 8). The nine least significant bits (HCF8-0) are the address for whatever is to be loaded (see Tables 9-14). For example, to load address 15 of the horizontal coefficient banks, the first data value into the LF InterfaceTM should be 00FH. To load horizontal limit register 10, the first data value should be C0AH. The first address value should be loaded into the interface on the same clock cycle that latches the HIGH to LOW transition of HLD (see Figures 12 and 13). FIGURE 14. COEFFICIENT BANK LOADING SEQUENCE WITH HPAUSE AND VPAUSE IMPLEMENTATION COEFFICIENT SET 1 CLK W1 HPAUSE/VPAUSE HLD/VLD HCF/VCF11-0 ADDR1 COEF0 COEF1 COEF7 W1: Coefficient Set 1 written to coefficient banks during this clock cycle. FIGURE 15. CONFIGURATION AND SELECT REGISTER LOADING SEQUENCE WITH HPAUSE AND VPAUSE IMPLEMENTATION CONFIGURATION REGISTER SELECT REGISTER CLK W1 HPAUSE/VPAUSE HLD/VLD W2 HCF/VCF11-0 ADDR1 DATA1 ADDR2 DATA1 W1: Configuration Register loaded with new data on this rising clock edge. W2: Select Register loaded with new data on this rising clock edge. Video Imaging Products 13 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter written into horizontal round register 12. Table 18 shows an example of loading data into a select register. Data value 00FH is loaded into horizontal select register 2. Table 19 shows an example of loading data into vertical limit register 7. Data value 390H is loaded as the lower limit and 743H is loaded as the upper limit. shows an example of loading data into a Configuration Register. Data value 003H is written into Configuration Register 4. Table 17 shows an example of loading data into a round register. Data value 7683F4A2H is FIGURE 16. ROUND REGISTER LOADING SEQUENCE WITH HPAUSE AND VPAUSE IMPLEMENTATION ROUND REGISTER CLK W1 HPAUSE/VPAUSE HLD/VLD HCF/VCF11-0 ADDR1 DATA1 DATA2 DATA3 DATA4 W1: Round Register loaded with new data on this rising clock edge. FIGURE 17. LIMIT REGISTER LOADING SEQUENCE WITH HPAUSE AND VPAUSE IMPLEMENTATION LIMIT REGISTER CLK W1 HPAUSE/VPAUSE HLD/VLD HCF/VCF11-0 ADDR1 DATA1 DATA2 W1: Limit Register loaded with new data on this rising clock edge. TABLE 15. COEFFICIENT BANK LOADING FORMAT H/VCF11 H/VCF10 H/VCF9 H/VCF8 H/VCF7 H/VCF6 H/VCF5 H/VCF4 H/VCF3 H/VCF2 H/VCF1 H/VCF0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 1 0 1 0 1 0 0 1 0 1 1 0 0 1 1st Word - Address 2nd Word - Bank 0 3rd Word - Bank 1 4th Word - Bank 2 5th Word - Bank 3 6th Word - Bank 4 7th Word - Bank 5 8th Word - Bank 6 9th Word - Bank 7 Video Imaging Products 14 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter all horizontal and vertical Round/ Limit registers can be updated in 3.08 s. The coefficient banks and Configuration/Control Registers are not loaded with data until all data values for the specified address are loaded into the LF InterfaceTM. In other words, the coefficient banks are not written to until all eight coefficients have been loaded into the LF InterfaceTM. A round register is not written to until all four data values are loaded. After the last data value is loaded, the interface will expect a new address value on the next clock cycle. After the next address value is loaded, data loading will begin again as previously discussed. As long as data is loaded into the interface, HLD must remain LOW. After all desired coefficient banks and Configuration/Control Registers are loaded with data, the LF InterfaceTM must be disabled. This is It takes 9S clock cycles to load S coefficient sets into the device. Therefore, it takes 2304 clock cycles to load all 256 coefficient sets. Assuming an 83 MHz clock rate, all 256 coefficient sets can be updated in 28.8 s, which is well within vertical blanking time. It takes 5S or 3S clock cycles to load S round or limit registers respectively. Therefore, it takes 256 clock cycles to update all round and limit registers (both horizontal and vertical). Assuming an 83 MHz clock rate, TABLE 16. CONFIGURATION REGISTER LOADING FORMAT H/VCF11 H/VCF10 H/VCF9 H/VCF8 H/VCF7 H/VCF6 H/VCF5 H/VCF4 H/VCF3 H/VCF2 H/VCF1 H/VCF0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1st Word - Address 2nd Word - Data TABLE 17. ROUND REGISTER LOADING FORMAT H/VCF11 H/VCF10 H/VCF9 H/VCF8 H/VCF7 H/VCF6 H/VCF5 H/VCF4 H/VCF3 H/VCF2 H/VCF1 H/VCF0 1 R R R R 0 R R R R 0 R R R R 0 R R R R 0 1 1 1 0** 0 0 1 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0* 0 1 0 1st Word - Address 2nd Word - Data 3rd Word - Data 4th Word - Data 5th Word - Data R = Reserved. Must be set to "0". * This bit represents the LSB of the Round Register. ** This bit represents the MSB of the Round Register. Video Imaging Products 15 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter zontal or Vertical LF InterfacesTM. Since both LF InterfacesTM operate independently of each other, both LF InterfacesTM can load data into their respective coefficient banks at the same time. Or, one LF InterfaceTM can load the Configuration/Control Registers while the other loads it's respective coefficient banks. If both LF InterfacesTM are used to load a configuration or control register at the same time, the Vertical LF InterfaceTM will be given priority over the Horizontal LF InterfaceTM. For example, if the Horizontal LF InterfaceTM attempts to load data into a Configuration Register at the same time that the Vertical LF InterfaceTM attempts to load a horizontal round register, the Vertical LF InterfaceTM will be allowed to load the round register while the Horizontal LF InterfaceTM will not be allowed to load the Configuration Register. However, the Horizontal LF InterfaceTM will continue to function as if the write occurred. done by setting HLD HIGH on the clock cycle after the clock cycle which latches the last data value. It is important that the LF InterfaceTM remain disabled when not loading data into it. The horizontal coefficient banks may only be loaded with the Horizontal LF InterfaceTM and the vertical coefficient banks may only be loaded with the Vertical LF InterfaceTM. The Configuration and Control Registers may be loaded with either the Hori- TABLE 18. SELECT REGISTER LOADING FORMAT H/VCF11 H/VCF10 H/VCF9 H/VCF8 H/VCF7 H/VCF6 H/VCF5 H/VCF4 H/VCF3 H/VCF2 H/VCF1 H/VCF0 1st Word - Address 2nd Word - Data 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 TABLE 19. LIMIT REGISTER LOADING FORMAT H/VCF11 H/VCF10 H/VCF9 H/VCF8 H/VCF7 H/VCF6 H/VCF5 H/VCF4 H/VCF3 H/VCF2 H/VCF1 H/VCF0 1st Word - Address 2nd Word - Data 3rd Word - Data 1 0* 0** 1 0 1 1 1 1 0 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 1 * This bit represents the MSB of the Lower Limit. ** This bit represents the MSB of the Upper Limit. Video Imaging Products 16 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... -65C to +150C Operating ambient temperature ........................................................................................... -55C to +125C VCC supply voltage with respect to ground ............................................................................ -0.5 V to +4.5 V Input signal with respect to ground .......................................................................................... -0.5 V to 5.5 V Signal applied to high impedance output ................................................................................. -0.5 V to 5.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA ESD Classification (MIL-STD-883E METHOD 3015.7) ...................................................................... Class 3 OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0C to +70C -55C to +125C Supply Voltage 3.00 V VCC 3.60 V 3.00 V VCC 3.60 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 CIN COUT Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent Input Capacitance Output Capacitance (Note 3) Test Condition VCC = Min., IOH = -4 mA VCC = Min., IOL = 8.0 mA Min 2.4 Typ Max Unit V 0.4 2.0 0.0 5.5 0.8 10 10 250 2 10 10 V V V A A mA mA pF pF Ground VIN VCC (Note 12) Ground VOUT VCC (Note 12) (Notes 5, 6) (Note 7) TA = 25C, f = 1 MHz TA = 25C, f = 1 MHz Video Imaging Products 17 11/08/2001-LDS.3310-H 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 8765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 9 Min DEVICES INCORPORATED * The `x' represents both horizontal and vertical signals for each case. COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns) SWITCHING WAVEFORMS: SWITCHING CHARACTERISTICS tENA tDIS tD tH1 tH0 tS1 tS0 tPWH tPWL tCYC xCEN, xRSL CONTROLS (Except OE) DOUT15-0 Parameter Three-State Output Enable Delay (Note 11) Three-State Output Disable Delay (Note 11) Output Delay Input Hold Time (xCEN, xRSL)* Input Hold Time Input Setup Time (xCEN, xRSL)* Input Setup Time Clock Pulse Width High Clock Pulse Width Low Cycle Time DIN11-0 HCA7-0 VCA7-0 CLK OE tS0 tS1 HCA/VCAN DINN tH0 tH1 1 DATA I/O HCA/VCAN+1 DINN+1 2 tDIS HIGH IMPEDANCE tPWH 3 tCYC tENA 1.5 25 10 10 tPWL 18 1 8 8 25* Horizontal / Vertical Digital Image Filter Max 15 15 13 4 Min 1.5 18 1 8 6 6 8 18* 5 Max 11 13 13 LF3310- Video Imaging Products Min 1.5 15 6 1 7 5 5 7 15 OUTPUTN-1 Max 10 12 12 tD 7 11/08/2001-LDS.3310-H Min OUTPUTN 1.5 12 1 5 4 4 5 LF3310 12 Max 10 10 8 432109876543210987654321 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE HPAUSE VPAUSE 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 98765432109876543210987654321 Min DEVICES INCORPORATED Symbol COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns) SWITCHING WAVEFORMS: HCF11-0 VCF11-0 tPH tPS tLH tLS tCFH tCFS HLD VLD CLK Parameter PAUSE Hold Time PAUSE Setup Time Load Hold Time Load Setup Time Coefficient Input Hold Time Coefficient Input Setup Time tCFS tLS ADDRESS tCFH 1 tPWH LF INTERFACETM tCYC CF0 tPWL 2 tPS 3 1.5 19 8 1 1 8 8 25* Horizontal / Vertical Digital Image Filter Max tPH Min 4 1.5 6 1 1 6 6 18* Max LF3310- Video Imaging Products CF1 tLH Min 1.5 5 5 1 1 5 5 15 Max 11/08/2001-LDS.3310-H Min 1.5 1.5 1.5 CF2 5 4 4 LF3310 12 6 Max LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and IOL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Never- used. Parasitic capacitance is 30 pF theless, conventional precautions minimum, and may be distributed. should be observed during storage, handling, and use of these circuits in This device has high-speed outputs caorder to avoid exposure to excessive pable of large instantaneous current electrical stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping testing of this device. The following of transient undershoot. Input levels measures are recommended: below ground will be clamped beginning at -0.6 V. The device can with- a. A 0.1 F ceramic capacitor should be stand indefinite operation with inputs installed between VCC and Ground or outputs in the range of -0.5 V to leads as close to the Device Under Test +5.5 V. Device operation will not be (DUT) as possible. Similar capacitors adversely affected, however, input cur- should be installed between device VCC rent levels will be well in excess of 100 and the tester common, and device mA. ground and tester common. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT socket or contactor fingers. anteed as specified. 5. Supply current for a given application can be accurately approximated by: NCV2 F c. Input voltages on a test fixture should be adjusted to compensate for inductive ground and VCC noise to maintain required DUT input levels relative to the DUT ground pin. 10. Each parameter is shown as a minimum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the 200mV level from the measured steady-state output voltage with 10mA loads. The balancing voltage, VTH, is set at 3.0 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 IOL CL IOH VTH DUT FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.0V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = -10mA and IOL = 10mA VOH* Measured VOH with IOH = -10mA and IOL = 10mA 4 where N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with outputs changing every cycle and no load, at a 40 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. Video Imaging Products 20 11/08/2001-LDS.3310-H LF3310 DEVICES INCORPORATED Horizontal / Vertical Digital Image Filter ORDERING INFORMATION 144-pin GND GND GND GND GND HCF11 HCF10 HCF9 HCF8 HCF7 HCF6 HCF5 HCF4 HCF3 HCF2 HCF1 HCF0 GND CLK VCC HLD GND VCC HPAUSE GND VCC HSHEN GND VCC TXFR VCC GND GND VCC VCC VCC VCC GND GND GND GND VCC GND DIN11 DIN10 DIN9 DIN8 DIN7 DIN6 GND VCC DIN5 DIN4 DIN3 DIN2 DIN1 DIN0 GND VCC VCA7 VCA6 VCA5 VCA4 VCA3 VCA2 VCA1 VCA0 VCEN VSHEN VCC VCC VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 Top View GND GND HCA7 HCA6 HCA5 HCA4 HCA3 HCA2 HCA1 HCA0 VCC GND HCEN GND VCC GND GND GND GND VCF11 VCF10 VCF9 VCF8 VCF7 VCF6 VCF5 VCF4 VCF3 VCF2 VCF1 VCF0 VLD VPAUSE VCC VCC VCC Speed Plastic Quad Flatpack (Q5) 0C to +70C -- COMMERCIAL SCREENING 15 ns 12 ns LF3310QC15 LF3310QC12 -55C to +125C -- COMMERCIAL SCREENING -55C to +125C -- MIL-STD-883 COMPLIANT GND VACC GND VRSL3 VRSL2 VRSL1 VRSL0 VCC GND NC NC NC NC DOUT11 DOUT10 DOUT9 DOUT8 GND OE DOUT7 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0 GND VCC GND HRSL3 HRSL2 HRSL1 HRSL0 HACC GND 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Video Imaging Products 21 11/08/2001-LDS.3310-H |
Price & Availability of LF3310QC15
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |